serial-bench - the whole archive

Five buses paid the rent: UART, SPI, I²C, CAN and RS-485. None is interesting until it breaks. This list was where I wrote up the breakages so the next dead line would not cost me the same afternoon twice.

Every figure here came off the scope or the analyser on my own desk; each message says which instrument produced it and what that instrument cannot do. Where the first reading was wrong - it happens - the message keeps the wrong number and explains what fooled me, because the mistake is usually the part worth keeping. No firmware tutorials, no parts recommendations, no thread of replies: it was a low-traffic announce list and the arguments happened off it, by mail to ivo@rawsocket.cloud.

Nine messages, Dec 2024 → Oct 2026

Browse: by date · by thread · by subject · grep

1. #9 10 Oct 2026 CAN Two nodes at 1 Mbit/s that sampled the bit in different places
   Same bit rate, same wire, properly terminated - and still a trickle of errors, because two controllers on their factory defaults were sampling the bit 125 ns apart. The time-quantum arithmetic, an oscillator-budget argument, and the layout I now set every node to.
2. #8 28 Sep 2026 CAN A 95-metre trunk that went quiet when I pulled one 120 Ω resistor
   Seventeen nodes, 500 kbit/s, and a single missing terminator. The bus did not die politely: it kept working for short frames and failed for long ones, which is the worst kind of symptom. With scope traces of the reflection and the arithmetic that predicts it.
3. #7 5 Aug 2026 I²C A sensor that held the clock low for 1.4 ms
   Worked from the bench script, returned garbage from the firmware, same board. The device was pausing the bus by holding SCL low during a conversion, and the product master's 25 µs clock timeout gave up on it. How to read a stretch apart from a wedged bus on the analyser.
4. #6 11 Jun 2026 UART Two boards agreed at 9600 and argued at 115200
   A 12 MHz crystal on one side, 11.0592 MHz on the other, and a table of divider errors that explains exactly where the receiver stops sampling inside the bit cell. The answer is not «use a better crystal».
5. #5 2 Mar 2026 I²C 310 pF of bus capacitance, and the rise time I kept ignoring
   Eleven devices on one segment, 1.8 kΩ pull-ups, and a bus that passed at 100 kHz but corrupted the last ACK at 400 kHz. How I measured the capacitance with nothing but a resistor and a stopwatch function.
6. #4 19 Nov 2025 RS-485 Four hundred metres between two buildings, and the ground that was not one
   A 19 200 bit/s half-duplex link that logged errors only in the morning. Measuring the potential difference between the two grounds, then rebuilding one end around an isolated transceiver and a separate supply.
7. #3 16 Sep 2025 SPI A SPI daisy chain where the last word came back short
   Three ADCs in series, one chip-select line, and the device at the far end losing its top two bits every single cycle. Ninety nanoseconds of propagation through the chain against a 125 ns bit, and the guard time that put it right.
8. #2 8 Jul 2025 SPI A mode mismatch reads like a one-bit shift, not like noise
   Every reading came back at exactly half its true value, which is a fingerprint rather than a symptom. Why slowing the clock made the wrong answer look plausible, and the timing diagram I now draw before touching any driver.
9. #1 14 Dec 2024 instruments My logic analyser lied to me for an afternoon
   The first entry on this list, and it is a confession: 24 MS/s against an 8 MHz clock gives three samples per bit, and I read the resulting ghost pulses as a hardware fault for four hours. What the sampling ratio has to be before a capture is evidence.

Posts landed when the bench actually surprised me, which worked out to roughly every other month. The Atom feed and JSON index carry the same nine entries for anything that wants to read them as data.